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september 2010 1 . features 256k x 36, 512k x 18 memory configurations supports high system speed: ? 150mhz 3.8ns clock access time lbo input selects interleaved or linear burst mode self-timed write cycle with global write control ( gw ), byte write enable ( bwe ), and byte writes ( bw x) 3.3v core power supply power down controlled by zz input 3.3v i/o supply (v ddq ) packaged in a jedec standard 100-pin thin plastic quad flatpack (tqfp) description the as8c803600/801800 are high-speed srams organized as 256k x 36, 512k x 18 3.3v synchronous srams 3.3v i/o, burst counter pipelined outputs, single cycle deselect as8c803600 as8c801800 256k x 36 / 512k x 18. the srams contain write, data, address and control registers. internal logic allows the sram to generate a self-timed write based upon a decision which can be left until the end of the write cycle. the burst mode feature offers the highest level of performance to the system designer, as the as8c803600/801800 can provide four cycles of data for a single address presented to the sram. an internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. the first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. if burst mode operation is selected ( adv =low), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. the order of these three addresses are defined by the internal burst counter and the lbo input pin. the as8c803600/801800 srams utilize the latest high-performance cmos process and are packaged in a jedec standard 14mm x 20mm 100- pin thin plastic quad flatpack (tqfp), a 0 -a 18 address inputs input synchronous ce chip enable input synchronous cs 0 , cs 1 chip selects input synchronous oe output enable input asynchronous gw global write enable input synchronous bwe byte write enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 (1) individual byte write selects input synchronous clk clock input n/a adv burst address advance input synchronous adsc address status (cache controller) input synchronous adsp address status (processor) input synchronous lbo linear / interleaved burst order input dc zz sleep mode input asynchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core power, i/o power supply n/a v ss ground supply n/a 5310 tbl 01 pin description summary note: 1. bw 3 and bw 4 are not applicable for other devices
6.42 2 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range symbol pin function i/o active description a 0 -a 18 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk and adsc low or adsp low and ce low. adsc address status (cache controller) i low synchronous address status from cache controller. adsc is an active low input that is used to load the address registers with new addresses. adsp address status (processor) i low synchronous address status from processor. adsp is an active low input that is used to load the address registers with new addresses. adsp is gated by ce . adv burst address advance i low synchronous address advance. adv is an active low input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. when the input is high the burst counter is not incremented; that is, there is no address advance. bwe byte write enable i low synchronous byte write enable gates the byte write inputs bw 1 - bw 4 . if bwe is low at the rising edge of clk then bw x inputs are passed to the next stage in the circuit. if bwe is high then the byte write inputs are blocked and only gw can initiate a write cycle. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. bw 1 controls i/o 0-7 , i/o p1 , bw 2 controls i/o 8-15 , i/o p2 , etc . any active byte write causes all outputs to be disabled. ce chip enable i low synchronous c h ip enable. ce is used with cs 0 and cs 1 to enable the idt71v67603/7803. ce also gates adsp . clk clock i n/a this is the clock input. all timing references for the device are made with respect to this input. cs 0 chip select 0 i high synchrono us active high chip select. cs 0 is used with ce and cs 1 to enable the chip. cs 1 chip select 1 i low synchronous active low chip select. cs 1 is used with ce and cs 0 to enable the chip. gw global write enable i low synchronous global write enable. this input w ill write all four 9-bit data bytes when low on the rising edge of clk. gw supersedes individual byte write enables. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a synchronous data input/output (i/o) pins. both the data input path and data output path are registered and triggered by the rising edge of clk. lbo linear burst order i low asynchronous burst order selection input. when lbo is high, the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input and must not change state while the device is operating. oe output enable i low asynchronous output enable. when oe is low the data output drivers are enabled on the i/o pins if the chip is also selected. when oe is high the i/o pins are in a high- impedance state. v dd power supply n/a n/a 3.3v core power supply. v ddq power supply n/a n/a 3.3v i/o supply. v ss ground n/a n/a ground. nc no connect n/a n/a nc pins are not electrically connected to the device. zz sleep mode i high asynchronous sleep mode input. zz high w ill gate the clk internally and power down the as8c803600/1800 to its lowest power consumption level. data retention is guaranteed in sleep mode. 53 10 tbl 02 pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk.
6.42 3 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range functional block diagram a 0? a 17/18 address register clr a1* a0* 18/19 2 18/19 a 2 ?a 18 256k x 36/ 512k x 18- bit memory array internal address a 0 ,a 1 bw 4 bw 3 bw 2 bw 1 byte 1 write register 36/18 36/18 adsp adv clk adsc cs 0 cs 1 byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver byte 2 write register byte 3 write register byte 4 write register 9 9 9 9 gw ce bwe lbo i/o 0 ?i/o 31 i/o p1 ?i/o p4 oe data input register 36/18 output buffer output register d q dq enable register enable delay register oe burst sequence cen clk en clk en q1 q0 2 burst logic binary counter 5301 drw 01 zz powerdown ,
6.42 4 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range 100 pin t qfp ca pacitance (t a = +25c, f = 1.0mhz) recommended operating temperature and suppl y voltage absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supplies have ramped up. power supply sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. recommended dc operating conditions note: 1. v il (min) = -1.0v for pulse width less than t cyc/2 , once per cycle. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating commercial unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 v t a (7) operating temperature -0 to +70 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 5 310 tbl 03 grade temperature (1) v ss v dd v ddq commercial 0c to +70c 0v 3.3v5% 3.3v5% industrial -40c to +85c 0v 3.3v5% 3.3v5% 5310 tbl 04 symbol parameter min. typ. max. uni t v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 3.135 3.3 3.465 v v ss supply voltage 0 0 0 v v ih input high voltage - inputs 2.0 ____ v dd +0.3 v v ih input high voltage - i/o 2.0 ____ v ddq +0.3 v v il input low voltage -0.3 (1) ____ 0.8 v 5 310 tb l 05 symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5310 tbl 07 119 bga capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input cap acitance v in = 3dv 7 pf c i/ o i/o cap acitance v out = 3dv 7 pf 5310 tbl 07a note: 1. t a is the "instant on" case temperature. symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/ o i/o capacitance v out = 3dv 7 pf 5310 tbl 07b 165 fbga capacitance (t a = +25c, f = 1.0mhz)
6.42 5 idt71v67603, idt71v67803, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial and industrial temperature ranges pin configuration C 256k x 36, 100-pin tqfp notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode. 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 b w 4 b w 3 b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a 1 7 n c n c n c l b o a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5301 drw 02 v dd /nc (1) i/o 15 i/o p3 nc i/o p4 a 1 5 a 1 6 i/o p1 nc i/o p2 zz (2) , top view
6.42 6 idt71v67603, idt71v67803, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial and industrial temperature ranges pin configuration C 512k x 18, 100-pin tqfp 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 n c n c b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c l b o a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5310 drw 03 v dd /nc (1) nc nc nc nc a 1 6 a 1 7 nc nc a 10 zz (2) , a 1 8 top view notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode.
6.42 7 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i lzz | zz and lbo input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a v ol output low voltage i ol = +8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -8ma, v dd = min. 2.4 ___ v 5310 tbl 0 8 dc electrical characteristics over the operating temperature and supply voltage range (1) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test load ac test conditions (v ddq = 3.3v) note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application and the zz pin will be internally pulled to v ss if not actively driven. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc while adsc = low; f=0 means no input lines are changing. 3. for i/os v hd = v ddq - 0.2v, v ld = 0.2v. for other inputs v hd = v dd - 0.2v, v ld = 0.2v. v ddq /2 50? i/o z 0 =50 ? 5310 drw 06 , 1 2 3 4 20 30 50 100 200 ? t cd (typical, ns) capacitance (pf) 80 5 6 5310 drw 07 , symbol parameter test conditions 166mhz 150mhz 133mhz unit com'l only com'l ind com'l ind i dd operating power supply current device selected, outputs open, v dd = max., v ddq = max., v in > v ih or < v il , f = f max (2) 340 305 325 260 280 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = 0 (2,3) 50 50 70 50 70 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = f max (2,3) 160 155 175 150 170 ma i zz full sleep mode supply current zz > v hd, v dd = max. 50 50 70 50 70 ma 5310 tbl 09 inp ut pulse le ve ls inp ut rise /fall time s inp ut timing re fe re nce le ve ls output timing reference levels ac test load 0 to 3v 2ns 1.5v 1.5v see figure 1 5 310 tbl 10
6.42 8 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range synchronous truth table (1,3) notes: 1. l = v il , h = v ih , x = don?t care. 2. oe is an asynchronous input. 3. zz = low for this table. operation address used ce cs 0 cs 1 adsp adsc adv gw bwe bw x oe (2) clk i/o de selected cycle, power down none h x x x l x x x x x - hi-z de selected cycle, power down none l x h l x x x x x x - hi-z de selected cycle, power down none l l x l x x x x x x - hi-z de selected cycle, power down none l x h x l x x x x x - hi-z de selected cycle, power down none l l x x l x x x x x - hi-z read cycle, begin burst external l h l l x x x x x l - d out read cycle, begin burst external l h l l x x x x x h - hi-z read cycle, begin burst external l h l h l x h h x l - d out read cycle, begin burst external l h l h l x h l h l - d out read cycle, begin burst external l h l h l x h l h h - hi-z write cycle, begin burst external l h l h l x h l l x - d in write cycle, begin burst external l h l h l x l x x x - d in read cycle, continue burst next x x x h h l h h x l - d out read cycle, continue burst next x x x h h l h h x h - hi-z read cycle, continue burst next x x x h h l h x h l - d out read cycle, continue burst next x x x h h l h x h h - hi-z read cycle, continue burst next h x x x h l h h x l - d out read cycle, continue burst next h x x x h l h h x h - hi-z read cycle, continue burst next h x x x h l h x h l - d out read cycle, continue burst next h x x x h l h x h h - hi-z write cycle, continue burst next x x x h h l h l l x - d in write cycle, continue burst next x x x h h l l x x x - d in write cycle, continue burst next h x x x h l h l l x - d in write cycle, continue burst next h x x x h l l x x x - d in read cycle, suspend burst current x x x h h h h h x l - d out read cycle, suspend burst current x x x h h h h h x h - hi-z read cycle, suspend burst current x x x h h h h x h l - d out read cycle, suspend burst current x x x h h h h x h h - hi-z read cycle, suspend burst current h x x x h h h h x l - d out read cycle, suspend burst current h x x x h h h h x h - hi-z read cycle, suspend burst current h x x x h h h x h l - d out read cycle, suspend burst current h x x x h h h x h h - hi-z write cycle, suspend burst current x x x h h h h l l x - d in write cycle, suspend burst current x x x h h h l x x x - d in write cycle, suspend burst current h x x x h h h l l x - d in write cycle, suspend burst current h x x x h h l x x x - d in 5310 tbl 11
9 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range linear burst sequence t able ( lbo =v ss ) synchronous write function t ruth table (1, 2) asynchronous truth table (1) interleaved burst sequence table ( lbo =v dd ) notes: 1. l = v il , h = v ih , x = don?t care. 2. bw 3 and bw 4 are not applicable other devices 3. multiple bytes may be selected during the same cycle. notes: 1. l = v il , h = v ih , x = don?t care. 2. synchronous function pins must be biased appropriately to satisfy operation requirements. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. operation gw bwe bw 1 bw 2 bw 3 bw 4 r e a d hhxxxx r e a d hl hhhh write all bytes l x x x x x write all bytes h l l l l l write byte 1 (3 ) hl l hhh write byte 2 (3 ) hl hlhh write byte 3 (3 ) hl hhl h write byte 4 (3 ) hl hhhl 5310 tbl 12 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11000110 5310 tbl 15 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11100100 5310 tbl 14 operation (2) oe zz i/o status power read l l data out active read h l high-z active write x l high-z ? data in active deselected x l high-z standby sleep mode x h high-z sleep 5310 tbl 13
6.42 10 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range ac electrical characteristics (v dd = 3.3v 5%, commercial and industrial temperature ranges) notes: 1. measured as high above v ih and low below v il . 2. transition is measured 200mv from steady-state. 3. device must be deselected when powered-up from sleep mode. 4. t cfg is the minimum time required to configure the device based on the lbo input. lbo is a static input and must not change during normal operation. 166mhz 150mhz 133mhz symbol parameter min. max. min. max. min. max. unit t cy c clock cycle time 6 ____ 6.7 ____ 7.5 ____ ns t ch (1) clock high pulse width 2.4 ____ 2.6 ____ 3 ____ ns t cl (1) clock low pulse width 2.4 ____ 2.6 ____ 3 ____ ns output parameters t cd clock high to valid data ____ 3.5 ____ 3.8 ____ 4.2 ns t cd c clock high to data change 1.5 ____ 1.5 ____ 1.5 ____ ns t cl z (2 ) clock high to output active 0 ____ 0 ____ 0 ____ ns t chz (2) clock high to data high-z 1.5 3.5 1.5 3.8 1.5 4.2 ns t oe output enable access time ____ 3.5 ____ 3.8 ____ 4.2 ns t olz (2 ) output enable low to output active 0 ____ 0 ____ 0 ____ ns t ohz (2) output enable high to output high-z ____ 3.5 ____ 3.8 ____ 4.2 ns set up times t sa address setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t ss address status setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sd data in se tup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sw write setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sav address advance setup time 1.5 ____ 1.5 ____ 1.5 ____ ns t sc chip enable/select setup time 1.5 ____ 1.5 ____ 1.5 ____ ns hold times t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hs address status hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw write hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hav address advance hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns sleep mode and configuration parameters t zzp w zz pulse width 100 ____ 100 ____ 100 ____ ns t zzr (3 ) zz recovery time 100 ____ 100 ____ 100 ____ ns t cf g (4 ) configuration set-up time 24 ____ 27 ____ 30 ____ ns 53 10 tb l 16

6.17 17 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range 100-pin plastic thin quad flatpack (tqfp) package diagram outline
618.42 19 as8c803600, as8c801800, 256k x 36, 512k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, single cycle deselect commercial temperature range 1. emlsi memory 2. device type 11. power 3. density 10. speed 4. function 9. package 5. technology 8. version 6. operating voltage 7. organization 1. emlsi memory 2. device type 11. power 3. density 10. speed 4. function 9. package 5. technology 8. version 6. operating voltage 7. organization alliance organ iza tion vcc range package operating temp speed mhz AS8C803600-QC150N 256k x 36 3.1 - 3.4v 100 pin t qfp comercial: 0 - 70c 150 as8c801800-qc150n 512k x 18 3.1 - 3.4v 100 pin tqfp comercial: 0 - 70c 150 ordering information ordering information alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 5.5v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial low power sram prefix 16 = x16 access time b = 48ball tfbga (-40 to + 85 c) n = lead free rohs compliant part part numbering system as8c 01= zbt q = 100 pin tqfp sync. sram prefix 18= x18 36 = x36 25 = flow- thru 0 ~ 70c 150mhz n= leadfree 80 = 8m 00 = pipelined speed 'hylfh &rqi 0rgh3dfndjh 2shudwlqj7hps1 ? alliance memory, inc. 551 taylor way, suite#1, san carlos , ca 94 070 tel: 6 50-610-6800 fax: 650- 620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved part number: as 8c803600/801800 document version: v. 1.0 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use.

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